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preliminary specifications cmos lsi LE28FV4001CTS-20 4m-bit (512k 8) flash eeprom *this product incorporate technology licensed from silicon storage technology, inc. this preliminary specification is subject to change without notice. sanyo electric co., ltd. semiconductor company 1-1, 1 chome, sakata, oizumi-machi, ora-gun, gunma, 370-0596 japan revision 2.20-february 23,2001-ay/ay-1/14 features cmos flash eeprom technology single 3.3-volt read and write operations sector erase capability: 256 bytes per sector fast access time: 200 ns low power consumption active current(read): 10 ma (max.) standby current: 15 a (max.) high read/write reliability sector-write endurance cycles: 10 4 10 years data retention latched address and data self-timed erase and programming byte programming: 40 s (max.) end of write detection:toggle bit/ data polling hardware/software data protection jedec standard byte-wide eeprom pinouts packages available le28fv4001cts: 32-pin tsop normal(8 14mm) product description the le28fv4001c is a 512k 8 cmos sector erase, byte program eeprom. the le28fv4001c is manufactured using sanyo's proprietary, high performance cmos flash eeprom technology. breakthroughs in eeprom cell design and process architecture attain better reliability and manufacturability compared with conventional approaches. the le28fv4001c erases and programs with a 3.3-volt only power supply. le28fv4001c conforms to jedec standard pinouts for byte wide memories and is compatible with existing industry standard eprom, flash eprom and eeprom pinouts. featuring high performance programming, the le28fv4001c typically byte programs in 30 s. the le28fv4001c typically sector (256 bytes) erases in 2ms. both program and erase times can be optimized using interface feature such as toggle bit or data polling to indicate the completion of the write cycle. to protect against an inadvertent write, the le28fv4001c has on chip hardware and software date protection schemes. designed, manufactured, and tested for a wide spectrum of applications, the le28fv4001c is offered with a guaranteed sector write endurance of 10 4 cycles. data retention is rated greater then 10 years. the le28fv4001c is best suited for applications that require reprogrammable nonvolatile mass storage of program or data memory. for all system applications, the le28fv4001c significantly improves performance and reliability, while lowering power consumption when compared with floppy diskettes or eprom approaches. eeprom technology makes possible convenient and economical updating of codes and control programs on-line. the le28fv4001c improves flexibility, while lowering the cost, of program and configuration storage applications. figure 1 shows the pin assignments for the 32 lead plastic tsop packages. figure 2 shows the functional block diagram of the le28fv4001c. pin description and operation modes can be found in tables 1 through 3. device operation commands are used to initiate the memory operation functions of the device. commands are written to the device using standard microprocessor write sequences. a command is written by asserting we low while keeping ce low. the address bus is latched on the falling edge of we , ce , whichever occurs last. the data bus is latched on the rising edge of we , ce , whichever occurs first. however, during the software write protection sequence the address are latched on the rising edge of oe or ce , whichever occurs first.
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 2/14 (top view) 32 pin tsop normal 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 oe a10 ce dq7 dq6 dq5 dq4 dq3 vss dq2 dq1 dq0 a0 a1 a2 a3 figure 1: pin assignments for 32-pin plastic tsop dq7-dq0 address buffers & latches x- decoder 4,194,304 bit superflash eeprom cell array y-decoder i/o buffers & data latches control logic a18-a0 ce oe we figure 2: functional block diagram of le28fv4001c
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 3/14 table 1: pin description symbol pin name functions a18-a0 address inputs to provide memory address. address are internally latched during write cycle. dq7-dq0 data input/output to output data during read cycle and receive i nput data during write cycles. data is internally latched during a write cycle. the outputs are in tri-state when oe or ce is high. ce chip enable to activate the device when ce is low. deselects and puts the device to standby when ce is high. oe output enable to activate the data output buffers. oe is active low. we write enable to activate the write operation. we is active low. v dd power supply to provide 3.3v 0.3v supply . v ss ground table 2: operation modes selection mode ce oe we dq address read v il v il v ih d out a in write v il v ih v il d in a in standby v ih xxhigh-z x write inhibit x v il x high-z / d out x xxv ih high-z / d out x product id v il v il v ih manufacturer code (bf) a18-a1=v il , a9=12v, a0=v il device code (04) a18-a1=v il , a9=12v, a0=v ih table 3: command summary command required setup command cycle execute command cycle sdp cycle operation address data operation address data sector_erase 2 write x 20h write sa d0h n byte_program 2 write x 10h write pa pd n reset 1 write x ffh y read_id 3 write x 90h read (7) (7) y software_data_unprotect (6) 7 software_data_protect (6) 7 definitions for table 3: 1. type definitions : x=high or low 2. address definitions : sa=sector address=a18-a8 ; sector size=256byte ; a7-a0=x for this command 3. address definitions : pa=program address=a18-a0 4. data definition : pd=program data, h=number in hex. 5. sdp=software data protect mode using 7-read-cycle-sequence. y=the operation can be executed with software data protect enabled. n=the operation cannot be executed with software data prote ct enabled. 6. refer to figure 11 and 12 for the 7-read-cycle-sequence software data protection. 7. address 0000h retrieves the manufacturer code of bf(hex), address 0001h retrieves the device code of 04(hex).
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 4/14 command definition table 3 contains a command list and a brief summary of the commands. the following is a detailed description of the options initiated by each command. the le28fv4001c has to have the software data unprotect sequence executed prior a byte program or erase in order to perform those functions. sector_erase operation the sector_erase operation is initiated by a setup command and an execute command. the setup command stages the device for electrical erasing of all bytes within a sector. a sector contains 256 bytes. this sector erasability enhances the flexibility and usefulness of the le28fv4001c, since most applications only need to change a small number of bytes or sectors, not the entire chip. the setup command is performed by writing (20h) to the device. to execute the sector-erase operation, the execute command (d0h) must be written to the device. the erase operation begins with the rising edge of the we pulse and terminated automatically by using an internal timer. see figure 8 for timing waveforms. the two-step sequence of a setup command followed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. sector_erase flowchart description fast and reliable erasing of the memory contents within a sector is accomplished by following the sector erase flowchart as shown in figure 3. the entire procedure consists of the execution of two commands. the sector_erase operation will terminate after a maximum of 4ms. a reset command can be executed to terminate the erase operation; however, if the erase operation is terminated prior to the 4ms time-out, the sector may not be completely erased. an erase command can be reissued as many times an necessary to complete the erase operation. the le28fv4001c cannot be ?overerased?. byte_program operation the byte_program operation is initiated by writing the setup command (10h). once the program setup is performed, programming is executed by the next we pulse. see figure 6 and 7 for timing waveforms. the address bus is latched on the falling edge of we , ce , or the rising edge of oe , whichever occurs first. the programming operation begins with either the rising edge of we , ce , whichever occurs first. the programming operation is terminated automatically by an internal timer. see the programming characteristics and waveforms for details, figures 4, 6 and 7. the two-step sequence of a setup command followed by an execute command ensures that only the addressed byte is programmed and other bytes are not inadvertently programmed. the byte_program flow chart description programming data into the device is accomplished by following the byte_program flowchart as shown in figure 3. the byte_program command sets up the byte for programming. the address bus is latched on the falling edge of we , ce , whichever occurs last. the data bus is latched on the rising edge of we , ce , whichever occurs first, and begins the program operation. the end of write can be detected using either the data polling or toggle bit. reset operation a reset command is provided as a means to safely abort the erase or program command sequences. following either setup command (erase or program) with a write of (ffh) will safely abort the operation. memory contents will not be altered. after the reset command, the device returns to the read mode. the reset command dose not enable write protect. see figure 10 for timing waveforms. read operation the read operation is initiated by setting ce , oe and we into the read mode. see figure 5 for read memory timing waveforms and table 2 for the read mode. read cycles from the host retrieve data from the array. the device remains enabled for read until another operating mode is accessed. during initial power-up, the device is in the read mode and is write protected. the device must be unprotected in order to execute a write operation the read operation is controlled by oe and ce at logic low. when ce is high, the chip is deselected and only standby power will be consumed. oe is the output control and is used to gate to the output pins. the data bus is in a high impedance state when either ce or oe is high.
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 5/14 read_id operation the read_id operation is initiated by writing a single command (90h). a read of address 0000h will outputs the manufacturer?s code (bfh). a read of address 0001h will outputs the device code (04h).any other valid command will terminate this operation. data protection from inadvertent writes in order to protect the integrity of nonvolatile data storage, the le28fv4001c provides hardware and software features to prevent writes to the device, for example, during system power-up or power-down. such provisions are described below. hardware write protection the le28fv4001c is designed with hardware features to prevent inadvertent writes. this is done in the following ways: 1. write inhibit mode: oe low, ce high or we high inhibit the write operation. 2. noise and glitch protection: write operations are initiated when the we pulse width is less than 15 ns. 3. after power-up the device is in the read mode and the device is in the write protect state. software data protection provisions have been made to further prevent inadvertent writes through software. in order to perform the write functions of erase or program, a two-step command sequence consisting of a setup command followed by an execute command avoids inadvertent erasing or programming of the device. the le28fv4001c will default to write protect after power-up. a sequence of seven consecutive reads at specified device addresses will unprotect the device. the address sequence is 1823h, 1820h, 1822h, 0418h, 041bh, 0419h, 041ah. the address has to be latched in the rising edge of oe or ce , whichever occurs first. a similar seven read sequence of 1823h, 1820h, 1822h, 0418h, 041bh, 0419h, 040ah will protect the device. also, refer to figure 11, 12 for the 7-read-sequence software write protection. the dq pins can be in any state (i.e., high, low, or high-z). end of write detection detection of where a write cycle ended is necessary to optimize system performance. the end of a write cycle (erase or program) can be detected by three means: 1) monitoring the data polling bit; 2) monitoring the toggle bit; 3) by two successive reads of the same data. these three detection mechanisms are described below. data polling (dq7) the le28fv4001c features data polling to indicate the and of a write cycle. during a write cycle, any attempt to read the last byte loaded will result in the complement of the loaded data on dq7. once the write cycle is completed, dq7 will show true data. see figure 13 for timing waveforms. in order for data polling to function correctly, the byte being polled must be erased prior to programming. toggle bit (dq6) an alternate means for determining the end of a write cycle is by monitoring the toggle bit dq6. during a write operation, successive attempts to read data from the device will result in dq6 toggling between logic "1" (high) and "0" (low). once the write cycle has completed, dq6 will stop toggling and valid data will be read. the toggle bit may be monitored any time during the write cycle. see figure 14 for timing waveforms. successive reads an alternate means for determining the end of a write cycle is by reading the same address for two consecutive data matches. product identification the product identification mode identifies the device and manufacturer as sanyo. this mode may be accessed by hardware or software operations. the hardware operation is typically used by an external programming to identify the correct algorithm for the sanyo le28fv4001c. users may wish to use the software operation to identify the device (i.e., using the device code). for details, see table 2 for the hardware operation. the manufacturer and device codes are the same for both operations. notes for operation during power up, the device?s state should be the write inhibition mode. (during power up, the device?s state should be ce =v ih or oe =v il or we =v ih ) if ce = we =v il and oe =v ih during power up, reset command should be asserted before operation.
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 6/14 start initial sector address execute two step sector erase command verify ff n y y n erase error sector erase completed last address? increment address read ff from device figure 3: sector_erase flowchart
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 7/14 start initialize addresses setup byte pro g ram command read end of write detection programming completed? n y n programming failure programming com p leted last address data verifies? next address l oa d add ress and data & start programming y y n figure 4: byte_program flowchart
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 8/14 absolute maximum stress ratings temperature under bias..........................................................-55 c ~ 125 c storage temperature................................................................-65 c ~ 150 c d.c. voltage on any pin to grand potential ...........................-0.5v ~ v cc +0.5v transient voltage (<20ns) on any pin to grand potential .......-1.0v ~ v cc +1.0v voltage on a9 to grand potential............................................-0.5v ~ 14.0v operating range ambient temperature..............................................................0 c ~ 70 c supply voltage (v dd ) .............................................................3.0v ~ 3.6v dc operating characteristics symbol parameter limit units test condition min. typ. max. i ccr power supply current (read) 10 ma ce = oe =v il , we =v ih , all dqs open address inputs=v ih / v il , at f=1/trc, v dd =v dd max. i ccw power supply current (write) 25 ma ce = we =v il , oe =v ih , v dd =v dd max. i sb2 standby v dd current (cmos input) 15 a ce =v dd -0.3v, v dd =v dd max. i li input leakage current 10 a v in =v ss ~v dd , v dd =v dd max. i lo output leakage current 10 a v out =vss~v dd , v dd =v dd max. v il input low voltage -0.3 0.6 v v dd =v dd max. v ih input high voltage 2.0 vcc+0.3 v v dd =v dd max. v ol output low voltage 0.4 v i ol =100 a, v dd =v dd min. v oh output high voltage 2.4 v i oh = -100 a, v dd =v dd min. power-up timing symbol parameter minimum units tpu_read power-up to read operation 10 ms tpu_write power-up to write operation 10 ms capacitance (ta=25 c , f=1mhz) symbol descriptions maximum units test condition c dq dq pin capacitance 12 pf v dq = 0v c in input capacitance 6 pf v in = 0v
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 9/14 ac characteristics read cycle timing parameters symbol parameter -20 units min. max. trc read cycle time 200 ns tce chip enable access time 200 ns taa address access time 200 ns toe output enable access time 100 ns tclz ce low to active output 0 ns tolz oe low to active output 0 ns tchz ce high to high-z output 60 ns tohz oe high to high-z output 60 ns toh output hold time 0 ns erase/program cycle timing parameters symbol parameter -20 units min. max. tse sector erase cycle time 4 ms tbp byte program cycle time 40 s tas address setup time 10 ns tah address hold time 50 ns tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time from we 10 ns toeh output enable hold time from we 10 ns tcp write pulse width ( ce ) 100 ns twp write pulse width 100 ns tcph ce high pulse width 50 ns twph we high pulse width 50 ns tds data setup time 50 ns tdh data hold time 10 ns trst reset command recovery time 4 s tpcp protect chip enable pulse width 100 ns tpch protect chip enable high time 150 ns tpas protect address setup time 40 ns tpah protect address hold time 100 ns note: this parameter is measured only for initial qualification and after a design or process change that could affect this par ameter. ac test conditions input load levels ....................................................................1ttl gate and cl=30pf input rise/fall time ................................................................10ns
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 10/14 figure 5: read cycle diagram a18-0 ce oe we dq7-0 trc tce toe tclz tolz data valid data valid toh taa tchz tohz figure 6: we controlled write cycle timing diagram a18-0 ce oe we dq7-0 tas tcs toes tah tch toeh twp twph tds tdh data valid
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 11/14 figure 7: ce controlled write cycle timing diagram a18-0 ce oe we dq7-0 tas toes tah tcph toeh tds tdh data valid tcp figure 8: sector erase timing diagram a18-0 dq7-0 we(ce) oe ce(we) setup command self-timed page erase cycle execute command (20h) tds tdh (d0h) tds tdh tse ain tas tah
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 12/14 figure 9: byte program timing diagram a18-0 dq7-0 we(ce) oe ce(we) setup command self-timed program cycle execute command (10h) tds tdh din tds tdh tbp ain tas tah figure 10: reset command timing diagram a18-0 dq7-0 we(ce) oe ce(we) reset command (ffh) tds tdh trst
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 13/14 figure 11: software data unprotect sequence address ce oe 1823 1820 tpas tpah 1822 tpcp tpch 0418 041b 0419 041a notes on figure 11 1. the address is latched on the rising edge of ce or we , whichever is earlier. 2. pins a16 to a18 should be at either v il or v ih figure 12: software data protect sequence address ce oe 1823 1820 tpas tpah 1822 tpcp tpch 0418 041b 0419 040a notes on figure 12 1. the address is latched on the rising edge of ce or we , whichever is earlier. 2. pins a16 to a18 should be at either v il or v ih
LE28FV4001CTS-20 4m-bit flash eeprom preliminary specifications sanyo electric co., ltd. 14/14 figure 13: data polling timing diagram (dq7) a18-0 ce oe we dq7 din=x dout=x dout=x dout=x toeh tce toe toes tbp an an an an figure 14: toggle bit timing diagram (dq6) a18-0 ce oe we dq6 toeh note tce toe toes note: this time interval signal can be tse or tbp, depending upon the selected operation mode.

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